A regenerative frequency divider, also known as a Miller frequency
divider, mixes the input signal with the feedback signal from the mixer.
A free-running oscillator which
has a small amount of a higher-frequency signal fed to it will tend to
oscillate in step with the input signal. Such frequency dividers were
essential in the development of television.
It operates similarly to an injection locked oscillator.
In an injection locked frequency divider, the frequency of the input
signal is a multiple (or fraction) of the free-running frequency of the
oscillator. While these frequency dividers tend to be lower power than
broadband static (or flip-flop based) frequency dividers, the drawback
is their low locking range. The ILFD locking range is inversely
proportional to the quality factor (Q) of the oscillator tank. In
integrated circuit designs, this makes an ILFD sensitive to process
variations. Care must be taken to ensure the tuning range of the driving
circuit (for example, a voltage-controlled oscillator) must fall within
the input locking range of the ILFD.
Digital dividers
For power-of-2 integer division, a simple binary counter can be used,
clocked by the input signal. The least-significant output bit alternates
at 1/2 the rate of the input clock, the next bit at 1/4 the rate, the
third bit at 1/8 the rate, etc. An arrangement of
flipflops are
a classic method for integer-n division. Such division is frequency and
phase coherent to the source over environmental variations including
temperature. The easiest configuration is a series where each flip-flop
is a divide-by-2. For a series of three of these, such system would be a
divide-by-8. By adding additional logic gates to the chain of flip
flops, other division ratios can be obtained. Integrated circuit logic
families can provide a single chip solution for some common division
ratios.
Another popular circuit to divide a digital signal by an even integer multiple is a Johnson counter. This is a type of shift register network
that is clocked by the input signal. The last register's complemented
output is fed back to the first register's input. The output signal is
derived from one or more of the register outputs. For example, a
divide-by-6 divider can be constructed with a 3-register Johnson
counter. The three valid values for each register are 000, 100, 110,
111, 011, and 001. This pattern repeats each time the network is clocked
by the input signal. The output of each register is a f/6 square wave
with 60° of phase shift between registers. Additional registers can be
added to provide additional integer divisors.
Mixed signal division (Classification: asynchronous sequential logic)
An arrangement of D flip-flops are
a classic method for integer-n division. Such division is frequency and
phase coherent to the source over environmental variations including
temperature. The easiest configuration is a series where each D
flip-flop is a divide-by-2. For a series of three of these, such system
would be a divide-by-8. More complicated configurations have been found
that generate odd factors such as a divide-by-5. Standard, classic logic
chips that implement this or similar frequency division functions
include the 7456, 7457, 74292, and 74294. (see List of 7400 series
integrated circuits)
Fractional-n dividers
Main article: Dual-modulus prescaler
A fractional-n frequency synthesizer can be constructed using two
integer dividers, a divide-by-n and a divide-by-(n + 1) frequency
divider. With a modulus controller, n is toggled between the two values
so that the VCO alternates
between one locked frequency and the other. The VCO stabilizes at a
frequency that is the time average of the two locked frequencies. By
varying the percentage of time the frequency divider spends at the two
divider values, the frequency of the locked VCO can be selected with
very fine granularity.
Delta-sigma fractional-n synthesizers
If
the sequence of divide by n and divide by (n + 1) is periodic, spurious
signals appear at the VCO output in addition to the desired frequency.
Delta-sigma fractional-n dividers overcome this problem by randomizing
the selection of n and (n + 1), while maintaining the time-averaged
ratios.
Binary Counters
Then we can see that a counter is nothing more than a specialised
register or pattern generator that produces a specified output pattern
or sequence of binary values (or states) upon the application of an
input pulse signal called the “Clock”.
The clock is actually used for data transfer in these applications.
Typically, counters are logic circuits that can increment or decrement a
count by one but when used as asynchronous divide-by-n counters they
are able to divide these input pulses producing a clock division signal.
Counters are formed by connecting flip-flops together and any number
of flip-flops can be connected or “cascaded” together to form a
“divide-by-n” binary counter where “n” is the number of counter stages
used and which is called the
Modulus. The modulus or simply “MOD”
of a counter is the number of output states the counter goes through
before returning itself back to zero, ie, one complete cycle.
Then a counter with three flip-flops like the circuit above will count from
0 to
7 ie,
2n-1. It has eight different output states representing the decimal numbers
0 to
7 and is called a
Modulo-8 or
MOD-8 counter. A counter with four flip-flops will count from
0 to
15 and is therefore called a
Modulo-16 counter and so on.
An example of this is given as.
- 3-bit Binary Counter = 23 = 8 (modulo-8 or MOD-8)
- 4-bit Binary Counter = 24 = 16 (modulo-16 or MOD-16)
- 8-bit Binary Counter = 28 = 256 (modulo-256 or MOD-256)
- and so on..
The Modulo number can be increased by adding more flip-flops to the
counter and cascading is a method of achieving higher modulus counters.
Then the modulo or MOD number can simply be written as:
MOD number = 2n
4-bit Modulo-16 Counter
Multi-bit asynchronous counters connected in this manner are also called
“Ripple Counters”
or ripple dividers because the change of state at each stage appears to
“ripple” itself through the counter from the LSB output to its MSB
output connection. Ripple counters are available in standard IC form,
from the 74LS393 Dual 4-bit counter to the 74HC4060, which is a 14-bit
ripple counter with its own built in clock oscillator and produce
excellent frequency division of the fundamental frequency.
is
an integer. Phase-locked loop frequency synthesizers make use of
frequency dividers to generate a frequency that is a multiple of a
reference frequency. Frequency dividers can be implemented for both analog and digital applications.
. This produces sum and difference frequencies 
at the output of the mixer. A low pass filter removes the higher frequency and the 
