Nah, sudah tau kan sedikit tentang bakteri ini, saya rasa hanya ini yang bisa saya sampaikan, lebih dan kurangnya saya mohon maaf, sampai jumpa lain waktu sob.. ^_^
untuk postingan saya yang lain silahkan klik disini.

     Asalamualaikum, Selamat pagi all... Dipostingan ini saya akan menjelaskan sedikit tentang Register geser ring counter. Register geser ring counter adalah rangkaian register geser yang dilengkapi dengan jaringan loop tertutup antara output Q flip-flop terakhir ke input pada flip-flop pertama. Jaringan loop tertutup pada register geser ini mengakibatkan terjadinya pergeseran data secara berurutan setiap pulsa clock diberikan secara terus menerus karena terjadi looping data. Kondisi seperti ini disebut sebagai keadaan “recirculates” sehingga register geser yang memiliki kondisi seperti ini disebut sebagai register geser ring counter. Rangkaian dasar ring counter dapat dilihat pada gambar berikut.

     Rangkaian register geser ring counter adalah register geser yang dilengkapi dengan jaringan umpan-balik dari data output terakhir ke jalur input flip-flop pertama. Rangkaian register geser ring counter diatas adalah register geser 4 bit yang disusun dari D-FF sehingga membentuk register geser ring counter 4 bit. Register geser ring counter dibuat denga data flip-flop (D-FF). Output dari rangkaian register geser ring counter diatas dapat digambarkan dalam timing diagram sebagai berikut.

Timing Diagram Register Geser Ring Counter 4 Bit

     Dari timing diagram diatas terlihat bahawa data yang diberikan ke rangkain register geser ring counter tersebut digeser ke posisi MSB kemudian umpankan kembali ke jalur input flip-flop pertama. Register geser ring counter ini sering digunakan atau diaplikasikan pada rangkaian kontrol kecepatan motor steper, rangkaian lampu berjalan dan rangkaian sequensial yang lain.

yah, mungkin hanya sebatas itu yang dapat saya sampaikan, lebih dan kurangnya saya mohon maaf, bila ananda dan kakanda masih samar-samar atau kurang jelas silahkan posting komentar di bawah. :D
Sekian dari saya, Assalamualaikum WRBR.

Timing diagram of Johnson Counter

A frequency divider, also called a clock divider or scaler or prescaler, is a circuit that takes an input signal of a frequency, , and generates an output signal of a frequency:

where  is an integer. Phase-locked loop frequency synthesizers make use of frequency dividers to generate a frequency that is a multiple of a reference frequency. Frequency dividers can be implemented for both analog and digital applications.

A regenerative frequency divider, also known as a Miller frequency divider, mixes the input signal with the feedback signal from the mixer.

The feedback signal is . This produces sum and difference frequencies ,  at the output of the mixer. A low pass filter removes the higher frequency and the  frequency is amplified and fed back into mixer.

A free-running oscillator which has a small amount of a higher-frequency signal fed to it will tend to oscillate in step with the input signal. Such frequency dividers were essential in the development of television.

It operates similarly to an injection locked oscillator. In an injection locked frequency divider, the frequency of the input signal is a multiple (or fraction) of the free-running frequency of the oscillator. While these frequency dividers tend to be lower power than broadband static (or flip-flop based) frequency dividers, the drawback is their low locking range. The ILFD locking range is inversely proportional to the quality factor (Q) of the oscillator tank. In integrated circuit designs, this makes an ILFD sensitive to process variations. Care must be taken to ensure the tuning range of the driving circuit (for example, a voltage-controlled oscillator) must fall within the input locking range of the ILFD.

Digital dividers

Mixed signal division (Classification: asynchronous sequential logic)

Fractional-n dividers
Main article: Dual-modulus prescaler

Delta-sigma fractional-n synthesizers

If the sequence of divide by n and divide by (n + 1) is periodic, spurious signals appear at the VCO output in addition to the desired frequency. Delta-sigma fractional-n dividers overcome this problem by randomizing the selection of n and (n + 1), while maintaining the time-averaged ratios.

Binary Counters

Then we can see that a counter is nothing more than a specialised register or pattern generator that produces a specified output pattern or sequence of binary values (or states) upon the application of an input pulse signal called the “Clock”.
The clock is actually used for data transfer in these applications. Typically, counters are logic circuits that can increment or decrement a count by one but when used as asynchronous divide-by-n counters they are able to divide these input pulses producing a clock division signal.
Counters are formed by connecting flip-flops together and any number of flip-flops can be connected or “cascaded” together to form a “divide-by-n” binary counter where “n” is the number of counter stages used and which is called the Modulus. The modulus or simply “MOD” of a counter is the number of output states the counter goes through before returning itself back to zero, ie, one complete cycle.
Then a counter with three flip-flops like the circuit above will count from 0 to 7 ie, 2ⁿ-1. It has eight different output states representing the decimal numbers 0 to 7 and is called a Modulo-8 or MOD-8 counter. A counter with four flip-flops will count from 0 to 15 and is therefore called a Modulo-16 counter and so on.

•   3-bit Binary Counter = 2³ = 8 (modulo-8 or MOD-8)
•   4-bit Binary Counter = 2⁴ = 16 (modulo-16 or MOD-16)
•   8-bit Binary Counter = 2⁸ = 256 (modulo-256 or MOD-256)
• and so on..

The Modulo number can be increased by adding more flip-flops to the counter and cascading is a method of achieving higher modulus counters. Then the modulo or MOD number can simply be written as: MOD number = 2ⁿ

4-bit Modulo-16 Counter

      Multi-bit asynchronous counters connected in this manner are also called “Ripple Counters” or ripple dividers because the change of state at each stage appears to “ripple” itself through the counter from the LSB output to its MSB output connection. Ripple counters are available in standard IC form, from the 74LS393 Dual 4-bit counter to the 74HC4060, which is a 14-bit ripple counter with its own built in clock oscillator and produce excellent frequency division of the fundamental frequency.

Tanks for reading my BLog  ^_^
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